1. Field of the Invention
The present invention generally relates to output driver circuits and, more particularly, to a programmable variable impedance output driver circuit which uses analog biases to match driver output impedance to load input impedance.
2. Description of the Related Art
In electronic systems, output drivers are required to drive I/O (input/output) devices and similar loads. In order to have efficient power transfer it is important that the impedance of the driver closely match the impedance of the load; the load comprising the impedance of the driven device as well as the impedance of the transmission line. Ideally, the driver impedance and the load impedance are equal. High performance output driver circuits require careful control of both current switching and output impedance characteristics. The former requirement, commonly referred to as dI/dt control, requires switching the driver on over a specified period of time, or switching multiple stages of the driver on in sequence. Such output current control techniques are necessary to minimize the on-chip inductive noise which occurs due to the large current requirements of the output driver circuits during switching. The driver impedance requirements result in "programmable impedance" drivers whose output resistance is varied using complicated digital controls. This impedance matching is necessary to avoid signal degradations due to bus reflections at high frequencies, where the output data bus acts as a transmission line. As product cycle times decrease, the current control and programmable impedance design points for an output driver must be carefully considered to avoid limiting the performance of the driver.
FIG. 1 illustrates a driver design for digitally varying the impedance of an output driver. The signals P-large, P-medium, P-small, and P-offset, control the number of PFETs, P10-P13, respectively, which are active when the driver is passing a high voltage value to the output signal node 14. Similarly, the signals N-large, N-medium, N-small, and N-offset control the number of NFETs, N20-N23, respectively, which are active when the driver is passing a low voltage value to the output signal node 14. The more FETs which are active when the output signal 14 is driven high or low, the lower the impedance of the driver. One control line 16 must be available for each FET. Each control line 16 is NANDed 26 or NORed 28 with the data signal 30 to activate the P-FET fingers or the NFET fingers, respectively. The discretization of possible driver impedance values is determined by the number of FETs. The smallest PFET and NFET dimensions available in a given technology determine the smallest impedance increments possible.
This approach has several disadvantages. First, to achieve fine impedance resolution, many FET controls must be applied to every driver, representing a significant amount of wiring. Second, any necessary dI/dt control must be implemented by staggering the switching of the FET controls. Because any binary combination of driver fingers is possible, the amount of turn-on/turn-off staggering which may occur is limited. This is true because the driver must have the same (or very nearly the same) turn-on/turn-off characteristics, independent of the programmed impedance. The only staggering which may thus occur is between an offset impedance (a FET width which must always be turned on, representing the highest possible impedance), and the remaining FET fingers. For example, in FIG. 1 the P-offset signal would switch independently before the P-large, P-medium, and P-small signals which all switch simultaneously some small amount of time later. This method provides minimal control of the switching current characteristics of the driver.
Finally, because the controls 18 are digital, they may only be changed at a time when the driver is disabled. If the controls 18 were to switch from a combination of P-large active, P-medium inactive, P-small inactive to a combination of P-large inactive, P-medium inactive, P-small active, it would be possible during that switching for all the FETs to be on or off at the same time. Such instances of large impedance changes are unacceptable when the driver is generating output. Thus a careful timing protocol is necessary between the programmable impedance control signal generation circuitry and the output driver.